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LT574A Complete 12-Bit A/D Converter
FEATURES
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DESCRIPTIO
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Industry-Standard 574A Compatible Complete 12-Bit A/D Converter with Reference and Clock Improved Reference Output Current Capability 25s Maximum Conversion Time Fast Bus Access Time 8- or 16-Bit Microprocessor Interface Guaranteed Linearity over Temperature
The LT(R)574A is a complete 12-bit A/D converter in the industry-standard 574A pinout. The three-state output buffers interface directly to an 8- or 16-bit microprocessor bus. A high precision 10V reference and clock are included on-chip, and the device provides full-rated performance without external circuitry or clock signals. The LT574A provides several advantages over other 574A type devices. External load driving capability of the reference has been improved to up to 8.5mA beyond the ADC current required. Maximum VCC has been increased to 22V and the reference can source full load current at a VCC of 11.4V without requiring an external buffer. The reference is trimmed to 10.00V with 0.2% maximum error and 5ppm/C typical TC. Bus timing specifications are significantly faster than original 574A specifications, easing microprocessor interface concerns.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATI
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Signal Processing Data Acquisition Process Monitoring and Control
TYPICAL PERFOR A CE
Integral Linearity
0.5 0.4 0.3
LINEARITY ERROR (LSB)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
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LT574A ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW V LOGIC 12/8 CS AO R/C CE VCC REF OUT AGND 1 2 3 4 5 6 7 8 9 28 STATUS 27 DB11 (MSB) 26 DB10 25 DB9 24 DB8 23 DB7 22 DB6 21 DB5 20 DB4 19 DB3 18 DB2 17 DB1 16 DB0 (LSB) 15 DGND NW PACKAGE 28-LEAD PDIP WIDE
VCC to Digital Common .................................. 0V to 22V VEE to Digital Common ............................. 0V to -16.5V VLOGIC to Digital Common ............................... 0V to 7V Analog Common to Digital Common ...................... 1V Digital Inputs to Digital Common.................... - 0.5V to VLOGIC + 0.5V Analog Inputs (REF In, BIP Off, 10VIN) to Analog Common................................ VEE to 16.5V 20VIN to Analog Common ............................. VEE to 24V REF Out ................. Indefinite Short to Analog Common Momentary Short to VCC Power Dissipation........................................... 1000mW Junction Temperature.......................................... 165C Operating Temperature Range J, K, L Grades ......................................... 0C to 70C Storage Temperature ........................... - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LT574AJNW LT574AKNW LT574ALNW
REF IN 10 VEE 11 BIP OFF 12 10VIN 13 20VIN 14
TJMAX = 100C, JA = 70C/ W
Consult factory for Industrial and Military grade parts.
CO VERTER ELECTRICAL CHARACTERISTICS
TA = 25C, VCC = 12V or 15V, VEE = - 12V, VLOGIC = 5V, unless otherwise specified.
PARAMETER Resolution Integral Linearity Error Differential Linearity Error (Minimum Resolution for Which No Missing Codes are Guaranteed) Unipolar Offset (Adjustable to Zero) Bipolar Offset (Adjustable to Zero) Full-Scale Calibration Error (With Fixed 50 REF Out to REF In (Adjustable to Zero) Temperature Coefficients Unipolar Offset Bipolar Offset Full-Scale Calibration Supply Sensitivity (Change in Full Scale Calibration) 13.5V VCC 16.5V or 11.4V VCC 12.6V - 16.5V VEE -13.5V or 12.6V VEE - 11.4V 4.5V VLOGIC 5.5V Input Ranges Unipolar Bipolar Input Impedance 10V Span 20V Span MIN
q q q
LT574AJ TYP MAX 12 1
MIN
LT574AK TYP MAX 12 0.5
MIN
LT574AL TYP MAX 12 0.5
11 2 4 10
12 1 4 10
12 1 2 4
UNITS Bits LSB Bits LSB LSB LSB
q q q q q q q q q q q q
2(10) 2(10) 9(50) 2.0 2.0 0.5 0 0 -5 - 10 3 6 5 10 10 20 5 10 7 14 0 0 -5 - 10 3 6 5 10
1(5) 1(5) 5(27) 1.0 1.0 0.5 10 20 5 10 7 14 0 0 -5 - 10 3 6 5 10
1(5) LSB(ppm/C) 1(5) LSB(ppm/C) 2(10) LSB(ppm/C) 1.0 1.0 0.5 10 20 5 10 7 14 LSB LSB LSB V V V V k k
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LT574A
I TER AL REFERE CE ELECTRICAL CHARACTERISTICS
PARAMETER REF OUT Voltage (No Load) Line Regulation, 11.4 VIN 22V
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Load Regulation (Sourcing Current), 0 IOUT 10mA
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Reference Temperature Coefficient
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER VLOGIC Supply Range VEE Supply Range VCC Supply Range VLOGIC Operating Current VEE Operating Current VCC Operating Current Power Dissipation Logic High Input Voltage Logic Low Input Voltage Logic Input Current Digital Input Pin Capacitance Logic Output Voltage Logic Low Output Voltage Leakage Current Output Capacitance CONDITIONS
q q q q q q q
VIH VIL IIN CIN VOH VOL COUT
The q denotes the specifications which apply over the full operating temperature range.
DIGITAL TI I G ELECTRICAL CHARACTERISTICS
TA = 25C, VCC = 15V, VEE = -15V, VLOGIC = 5V, unless otherwise specified.
SYMBOL tDD tHD tHL tSSR tSRR tSAR tHSR tHRR tHAR PARAMETER Access Time (from CE) Data Valid After CE Low Output Float Delay CS-to-CE Setup R/C-to-CE Setup AO-to-CE Setup CS Valid After CE Low R/C High After CE Low AO Valid After CE Low LT574A, All Grades MIN TYP MAX 75 150 25 150 50 0 50 50 0 50 UNITS ns ns ns ns ns ns ns ns ns
Read Timing, Full Control Mode
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MIN 9.98
q
LT574AJ TYP MAX 10.02 1 5 10 12 30 50 50
MIN 9.98
LT574AK TYP MAX 10.02 1 5 10 12 30 50 27
MIN 9.99
LT574AL TYP MAX 10.01 1 5 10 12 30 50 10
UNITS V ppm/V ppm/V ppm/mA ppm/mA ppm/C
12/8, CE, AO, R/C, CE 12/8, CE, AO, R/C, CE
q q q
ISOURCE 600A ISINK 1.6mA High-Z State
LT574A, All Grades MIN TYP MAX 4.5 5.0 5.5 - 11.4 - 16.5 11.4 22.0 27 40 - 15 - 25 1.7 3.5 390 700 2.0 5.5 - 0.5 0.8 - 100 100 5 2.4 0.4 - 20 20 5
UNITS V V V mA mA mA mW V V A pF V V A pF
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LT574A
DIGITAL TI I G ELECTRICAL CHARACTERISTICS
TA = 25C, VCC = 15V, VEE = -15V, VLOGIC = 5V, unless otherwise specified.
SYMBOL tDSC tHEC tSSC tHSC tSRC tHRC tSAC tHAC tC PARAMETER STS Delay from CE CE Pulse Width CS-to-CE Setup CS Low During CE High R/C-to-CE Setup R/C Low During CE High AO-to-CE Setup AO Valid During CE High Conversion Time 8-Bit Cycle 12-Bit Cycle Low R/C Pulse Width STS Delay From R/C Data Valid After R/C Low STS Delay After Data Valid High R/C Pulse Width Data Access Time LT574A, All Grades MIN TYP MAX 200 50 50 50 50 50 0 50 10 15 50 25 25 150 17 25 200 600 150 UNITS ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns
Convert Start Timing, Full Control Mode
Stand-Alone Mode Timing
BLOCK DIAGRA
+VLOGIC 12/8 CS AO R/C CE +VCC REF OUT ANALOG COMMON 1 2 3 4 5 6 7 8
THREE-STATE OUTPUT BUFFERS
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REF IN -VEE BIP OFF AIN 10V AIN 20V
10 11 12 13 14
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tHRL tDS tHDR tHS tHRH tDDR
28 27 26 CONTROL LOGIC CLOCK 12 BITS 10.00V REFERENCE LT1021-10 NIB A 25 24 23 22 NIB B 21 20 19 NIB C 18 17 16 15 19.95k 12-BIT DAC
STATUS DB11 (MSB) DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) DIGITAL COMMON
SUCCESSIVE APPROXIMATION REGISTER
12 BITS
9.95k 5k 5k
+
COMPARATOR
-
574A F01/BD
Figure 1. LT574A Block Diagram
LT574A
DISCUSSIO OF SPECIFICATIO S
Integral Linearity Error Integral linearity (INL) error refers to the deviation of each code from a theoretical line drawn from "full scale." Zero is defined as the input voltage occurring 0.5LSB (1.22mV for 10V full scale) before the first code transition (0 to 1) and "full scale" is defined as the voltage occurring 1.5LSB beyond the last code transition (4094 to 4095). Differential Linearity Error A guaranteed "no missing codes" specification requires that every code combination appears in a monotonically increasing sequence. Thus LT574A grades which guarantee no missing codes to 12-bit resolution have a maximum DNL error of 1LSB; grades which guarantee no missing code to an 11-bit level means that all code combinations of the upper 11 bits are present. In practice very few of the 12-bit codes are missing on the lower grade(s). Unipolar Offset Unipolar offset error is defined as the deviation of the first code transition from a level 0.5LSB above analog common. Unipolar offset can be adjusted as shown on the following pages. The unipolar offset temperature coeffiFEEDBACK TO AMPLIFIER
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CURRENT LIMITING RESISTORS
V-
IIN IS MODULATED BY CHANGES IN TEST CURRENT. AMPLIFIER PULSE LOAD RESPONSE LIMITED BY OPEN-LOOP OUTPUT IMPEDANCE.
ANALOG COMMON
574A F02
Figure 2. Op Amp/LT574A Interface
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cient specifies the change of the first transition value versus a change in ambient temperature. Bipolar Offset The major carry transition (2047 to 2048) should occur for an analog value 0.5LSB above analog common in the bipolar mode. Bipolar offset error can also be adjusted as shown on the following pages. The bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error versus temperature. Quantization Uncertainty Analog-to-digital converters have inherent quantization uncertainty of 0.5LSB. This uncertainty is a fundamental property of the conversion process and cannot be reduced for a converter of a given resolution. Left-Justified Data The LT574A uses a left-justified data format. The analog input is represented as a fraction of full scale, ranging from 0 to 4095/4096. A binary point to the left of the MSB is implied.
LT574A IIN RIN ITEST CURRENT OUTPUT DAC COMPARATOR
IDIFF
SAR
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LT574A
DISCUSSIO OF SPECIFICATIO S
Full-Scale Calibration Error The last output code transition (4094 to 4095) should occur for an analog value 1.5LSB below the nominal full scale (9.9963V for 10.000V full scale). The deviation of the actual level at which this transition occurs from the ideal level is the full-scale calibration error. Typically less than 0.1% of full scale, this error can be adjusted to zero as shown in Figures 3 and 4. Temperature Coefficients The temperature coefficients for unipolar offset, bipolar offset and full-scale calibration specify the maximum change from the nominal (25C) value to TMIN or TMAX. Power Supply Sensitivity The LT574A is specified using 5V and 15V or 12V supplies. The major effect of power supply voltage deviations from the rated values will be a small change in fullscale calibration. This change results in a proportional change in all code values. Code Width Code width is defined as the range of analog values for which a given output code will occur. The ideal value of a code width is equivalent to 1LSB (least significant bit) of the full-scale range. In a 10V full-scale range one LSB corresponds to 2.44mV.
-12V TO -15V OFFSET R1 100k 12V TO 15V GAIN 100k 10 R2 100 8 12 13 0V TO 10V ANALOG INPUTS 0V TO 20V 10VIN 14 REF IN REF OUT BIP OFF LT574A
OPERATIO
Circuit Operation
The LT574A provides the complete 12-bit analog-to-digital function with no external components. A block diagram of the LT574A is shown in Figure 1. After a conversion is initiated via the control section (described later) the clock is enabled and the SAR is set to 1000 0000 0000. Once a conversion is started it cannot be stopped or restarted. The output buffers go into the Hi-Z state. The SAR, driven by the internal clock, will sequence through the conversion cycle and return a signal indicating end-of-conversion to the control section. The control section then
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100
20VIN DIGITAL 15 COMMON
9 ANALOG COMMON
574A F03
Figure 3. Unipolar Input Connections
GAIN R2 100 R1 100 OFFSET 5V ANALOG INPUTS 10V
10 8 12 13
REF IN REF OUT BIP OFF LT574A 10VIN
14
20VIN DIGITAL 15 COMMON
9 ANALOG COMMON
574A F04
Figure 4. Bipolar Input Connections
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disables the clock, bring the Status output low, and enables control functions to allow data read functions via external command. During a conversion, the internal 12-bit current-output DAC is sequenced by the SAR starting with the most significant bit (MSB) and ending with the least significant bit (LSB). At the end of the process the DAC outputs a current which accurately balances the input signal current through the 5k (10k) input resistor. The comparator looks at the summing node at every bit test. If the DAC current sum is greater than the input current, the bit is turned off;
LT574A
OPERATIO
if less, the bit is left on. After all 12 bits have been tested, the SAR contains a 12-bit digital representation of the analog input signal accurate to 12 bits 0.5LSB. Two 5k input scaling resistors allow either 10V or 20V span operation. The 10k bipolar offset resistor is connected to the 10V reference for bipolar operation, or grounded for unipolar operation. Internal 10.00V Reference An LT1021-10 low noise, high stability, buried-zener reference is used inside the LT574A device and guarantees superior stability over time and temperature. This reference provides improved performance over other 574-type references in both voltage range and output current sourcing capability. The reference is trimmed to 10.00V 2%. It can supply up to 8.5mA to an external load in addition to the current required by the reference input resistor (0.5mA) and the bipolar offset resistor (1mA). This is an additional 7mA over most other 574A-type devices. (The external load should not change during a conversion.) The LT574A also has an improved VCC supply range; the VCC input can range from 11.2V to 22V. If operating from 12V supplies, improved driving capability eliminates the need for an external buffer to source external loads at room temperature or over the specified temperature range. Driving the LT574A Analog Inputs The signal source driving the LT574A input looks into a 5k or 10k impedance. However, the current drawn out of the input pins is abruptly modulated as the ADC steps through the bit tests. Low source impedance at high frequency, necessary to hold the input voltage constant through the conversion cycle, is required for 12-bit accurate conversions. The output impedance of an op amp is equal to its open-loop output impedance divided by the loop gain available at the frequency of interest. Acceptable loop gain at 500kHz is needed for use with the LT574A. An op amp can be checked for suitability by monitoring the LT574A's input with an oscilloscope while a conversion is in progress. Each of the 12 disturbances should settle in 1s or less. Suitable op amps include the LT1055 or LT1122.
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Layout Precautions and Supply Decoupling It is critically important the LT574A power supplies be well regulated and free of high frequency noise. Noisy supplies will cause unstable output codes. If switching power supplies must be used, considerable care must be used to ensure that switching spikes are eliminated. (For more information on constructing switching power supplies suitable for use with precision analog circuits, please see Linear Technology's Application Note 29). Just a few millivolts of high frequency noise on the power supply will result in several counts of error. Decoupling capacitors should be used on all power supply pins. VLOGIC decoupling should be connected directly from pin 1 to pin 15 (digital common) and VCC and VEE pins should be decoupled directly to analog common (pin 9). A 4.7F tantalum unit in parallel with a 0.1F ceramic type makes a suitable decoupling capacitor. The LT574A should be located as far as possible from digital circuitry on the board layout. Coupling between analog and digital lines should be minimized. If analog and digital lines must cross, they should do so at right angles. Parallel analog and digital lines should be separated by a pattern connected to common. Wire-wrap construction is not recommended; careful printed circuit layout is preferred instead. Grounding Considerations The analog common (pin 9) is the internal reference ground and should be connected directly to the analog reference point of the system. It is the "high quality" ground point. Pin 9 should be connected to digital common (pin 15) at the package to achieve all the high performance accuracy available from the LT574A in noisy digital environments. This single-point grounding is the preferred method for grounding mixed analog/digital systems. Be sure there are no digital ground returns on the analog side of the line; input signal returns should be isolated from digital ground and returned directly to the single-point ground at the LT574A package.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT574A
OPERATIO
Range Connections The LT574A has four standard input ranges: 0V to 10V, 0V to 20V, - 5V to 5V, and - 10V to 10V. To use the 10V range, connect the input signal between pins 13 and 9. To use the 20V range, connect the input signal between pins 14 and 9. In both cases, the other pin of the two is left unconnected. Full-scale and offset adjustments are shown in Figure 3. If full-scale trim is not needed, connect a 50, 1% metal film resistor between pins 8 and 10. To extend the 10V range to 10.24V (2.5mV/bit) with gain trim potentiometer (R2) should be replaced by a 50 resistor and a 200 potentiometer should be placed in series with the 10VIN pin. To obtain a full-scale range of 20.48V (5mV/bit), a 500 potentiometer should be used in series with pin 14. Gain trim is now implemented with these potentiometers. Unipolar Calibration The first transition of the LT574A occurs at a value 0.5LSB above analog common, so that the exact analog input for a given code will be halfway between the code transitions.
PACKAGE DESCRIPTION
0.600 - 0.625 (15.240 - 15.875)
0.009 - 0.015 (0.229 - 0.381) +0.025 0.625 -0.015 +0.635 -0.381
(
15.87
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
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This 0.5LSB offset is built into the LT574A. The unit will behave in this manner, within specifications, if pin 12 is connected to analog common (pin 9). Referring to Figure 3, R1 performs the offset adjust function. It should be adjusted so that the first transition falls at exactly 0.5LSB above the analog common potential (nominally ground). The circuit, as shown, will give approximately 15mV of offset trim range. The full-scale trim is calibrated by applying a voltage 1.5LSB below full scale (9.9963V for 10V full scale) and adjusting R2 such that the unit outputs the codes 4096 and 4097 (1111 1111 1110 and 1111 1111 1111). Bipolar Operation Bipolar operation connections are shown in Figure 4. The trim potentiometers can be replaced by 50, 1% resistors if offset and gain specifications are sufficient. To calibrate, apply an input signal 0.5LSB above negative full scale (0000 0000 0000 to 0000 0000 0001), then apply a signal 1.5LSB below positive full scale (4.9963V for the 5V range) and adjust R2 so that the last transition (1111 1111 1110 to 1111 1111 1111) is output.
Dimensions in inches (millimeters) unless otherwise noted. N Package 28-Lead Plastic DIP
1.455* (36.957) MAX 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.505 - 0.560* (12.827 - 14.224) 1 0.150 0.005 (3.810 0.127) 2 3 4 5 6 7 8 9 10 11 12 13 14 0.045 - 0.065 (1.143 - 1.651) 0.015 (0.381) MIN 0.070 (1.778) TYP 0.125 (3.175) MIN 0.035 - 0.080 (0.889 - 2.032) 0.100 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076)
N28 0594
LT/GP 1294 2K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1993

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